1. Field of the Invention
The present invention relates to a circuit board, a fabricating method thereof and a package structure, and more particularly, to a circuit board which lead has a bump disposed thereon, and a fabricating method thereof and a package structure.
2. Description of the Prior Art
Flip-chip packaging processes are one of the most popular electronic packaging processes utilized today. In contrast to the some other packaging processes, the chips utilized in the flip-chip packaging processes are not electrically connected to a packaging substrate via a bonding pad through a wire bonding process. Instead, a plurality of gold bumps are respectively formed on each bonding pads. Then, the chips are inverted and an anisotropic conductive film or silver paste is utilized to adhere the gold bumps to a package substrate. Ideally, flip-chip packaging processes are able to significantly reduce the size of package structures and increase the circuit transmission between the chips and the packaging substrate because no extra wires are required for establishing a connection.
Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a chip with a gold bump according to the prior art. As shown in FIG. 1, a chip 10 includes a chip substrate 12, a bonding pad 14, a protective layer 16, and a gold bump 18. The bonding pad 14 is disposed on the chip substrate 12, and the protective layer 16 covers the chip substrate 12 and a part of the bonding pad 14. The gold bump 18 is disposed on the bonding pad 14 and in contact with the bonding pad 14. Furthermore, in order to avoid the chip substrate 12 from being in contact with the package substrate when the chip 10 is bonding onto the package substrate, the gold bump 18 has a height between 12 micrometers and 15 micrometers.
However, the gold bump is formed by gold, and the price of gold gradually rises and is expensive. Thus, the fabricating cost of bonding the chip onto the package substrate is gradually increased. Hence, it has become an important task in this field to reduce the fabricating cost of bonding the chip onto the package substrate.